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Maxim Integrated
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with SPI Interface
MAX5214/MAX5216
Figure 1. 16-Bit Serial-Interface Timing Diagram (MAX5214)
Figure 2. 24-Bit Serial-Interface Timing Diagram (MAX5216)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to +105NC, unless otherwise noted. Typical values are
at TA = +25NC.) (Note 2)
Note 2: Electrical specifications are production tested at TA = +25NC and TA = +105NC. Specifications over the entire operating
temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25NC and are not
guaranteed.
Note 3: Static accuracy tested without load.
Note 4: Linearity is tested within 20mV of GND and VDD.
Note 5: Gain and offset is tested within 100mV of GND and VDD.
Note 6: Subject to offset and gain error limits and VREF settings.
Note 7: Guaranteed by design; not production tested.
Note 8: All timing specifications measured with VIL = VGND, VIH = VDD.
DIN15
123
45
1
67
8
14
15
16
DIN14
DIN13
tDS
tDH
tCP
DIN12
DIN11
DIN10
DIN9
DIN8
DIN2
DIN1
DIN0
DIN15
DIN
SCLK
CS
tCSH0
tCH
tCL
tCSS0
tCSA
tCLPW
tCSC
tCSF
tCSPW
CLR
tCSH1
DIN23
DIN22
DIN21 DIN20
DIN19
DIN18 DIN17
DIN16
DIN2
DIN1
DIN0
DIN23
123
45
67
8
22
23
24
1
DIN
SCLK
CS
tCSH1
tCSA
tCSF
tCLPW
tCSC
tCSPW
CLR
tDS
tDH
tCP
tCH
tCL
tCSH0
tCSS0
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLR Pulse-Width Low
tCLPW
20
ns
CLR Rise to CS Fall
tCSC
20
ns
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